Fast-locking phase locked loop and fast locking method
US10541695B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Sep 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fast-locking phase locked loop and a fast locking method are provided. The fast locking method includes dividing a frequency of an oscillation signal by a preset divisor to output a divided signal, detecting a frequency difference between the divided signal and a reference signal, tracking whether a divided frequency of the divided signal falls within a locked frequency range or not, if not, tracking the divided frequency, and if yes, locking the divided frequency, detecting a divided phase difference between a divided phase of the divided signal and a reference phase of the reference signal, recording the phase difference as a tracking reference phase difference, tracking a next divided phase according to the tracking reference phase difference, and determining whether the divided phase falls within a locked phase range, and if not, tracking the divided phase, and if yes, locking the divided phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.