Detecting stale memory addresses for a network device flow cache
US10541918B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2018 |
| Grant date | Jan 21, 2020 |
| Priority date | — |
| Expiry date | Mar 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/54
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An example network device includes a flow cache configured to store a flow cache entry that indicates a memory address referenced by one or more actions of the flow cache entry and a first learn index for the memory address, a memory address map configured to store a second learn index for the memory address, and one or more processors implemented in circuity. The network device is configured to receive a packet for the flow and obtain, from the flow cache entry for the flow, the memory address referenced by the one or more actions and the first learn index. The network device is further configured to determine the first learn index matches the second learn index and forward, in response to the determining, the packet using the one or more actions of the flow cache entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.