Memory controller, memory system, and memory controller control method
US10545804B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2015 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Apr 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
[Object] To sufficiently reduce frequency of error occurrence in memory cells.[Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.