Coordination of cache and memory reservation
US10545871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2019 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Apr 22, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for coordinating cache and memory reservation in a computerized system includes identifying at least one running application, recognizing the at least one application as a latency-critical application, monitoring information associated with a current cache access rate and a required memory bandwidth of the at least one application, allocating a cache partition, a size of the cache partition corresponds to the cache access rate and the required memory bandwidth of the at least one application, defining a threshold value including a number of cache misses per time unit, determining a reduction of cache misses per time unit, in response to the reduction of cache misses per time unit being above the threshold value, retaining the cache partition, assigning a priority of scheduling memory request including a medium priority level, and assigning a memory channel to the at least one application to avoid memory channel contention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.