Patent · US Active

System, method, and computer program product for improving coverage accuracy in formal verification

US10546083B1 · kind B1 · utility

1Cited by

6References

18Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Amit Verma · Schweinhub, DE
Suyash Kumar · Sidhauli, IN
Habeeb Farah · Nazareth, IL

Key dates

Filing date	May 10, 2017
Grant date	Jan 28, 2020
Priority date	—
Expiry date	May 11, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D89/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and automatically identifying one or more code coverage points from a netlist of an original model associated with the electronic design. Embodiments may include receiving a property and one or more elements, each of the one or more elements corresponding to one of the one or more code coverage points. Embodiments may further include performing model checking based upon, at least in part, the property and the one or more elements. Embodiments may also include verifying the property and generating an unsatisfiability core based upon, at least in part, the one or more elements.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.