Resistive memory device having memory cell array and system including the same
US10546623B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Nov 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.