Post package repair for mapping to a memory failure pattern
US10546649B2 · kind B2 · utility
5Cited by
24References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 18, 2015 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Sep 30, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one example in accordance with the present disclosure, a method includes mapping, using post-package repair, an address associated with a first memory row of a computing device to a spare memory row of the computing device, wherein the spare memory row has a memory failure pattern, and reading data from the spare memory row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.