Self-aligned via below subtractively patterned interconnect

US10546772B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Manish Chandhok · Beaverton, US
• Richard E. Schenker · Portland, US
• Hui Jae Yoo · Hillsboro, US
• Kevin Lin · Beaverton, US
• Jasmeet S. Chawla · Hillsboro, US
• Stephanie A. Bojarski · Beaverton, US
• Satyarth Suri · Hillsboro, US
• Colin T. Carver · Hillsboro, US
• Sudipto Naskar · Portland, US

Key dates

• Filing date: Mar 30, 2016
• Grant date: Jan 28, 2020
• Expiry date: Mar 30, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/53271
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.