Trench MOS device with improved single event burn-out endurance
US10546951B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 17, 2016 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Oct 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/144
Abstract
A trench MOS device with improved single event burnout endurance, applied in the field of semiconductor. The device is provided, in an epitaxial layer, with a conductive type semiconductor pillar connected to a source and a second conductive type current-directing region. Whereby, the trajectory of the electron-hole pairs induced by the single event effect is changed and thus avoids the single event burnout caused by the triggering of parasitic transistors, therefore improving the endurance of the single event burnout of the trench MOS device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.