Background calibration of reference, DAC, and quantization non-linearity in ADCS
US10547319B2 · kind B2 · utility
3Cited by
8References
37Claims
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Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Jan 28, 2020 |
| Priority date | — |
| Expiry date | Sep 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multi-step ADCs performs multi-step conversion by generating a residue for a subsequent stage to digitize. To generate a residue, a stage in the multi-step ADC would reconstruct the input signal to the stage using a feedforward digital to analog converter (DAC). Non-linearities in the DAC can directly affect the overall performance of the multi-step ADC. To reduce power consumption and complexity of analog circuit design, digital background calibration schemes are implemented to address the non-linearities. The non-linearities that the calibration schemes address can include reference, DAC, and quantization non-linearities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.