Voltage regulator efficiency-aware system energy management
US10551900B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jul 25, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.