Core frequency management using effective utilization for power-efficient performance
US10551901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jan 18, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A frequency governing method for a processor includes reading power management information from the processor. The processor operates in an active state or one of multiple power saving states. The power management information includes first information indicating occupancy of a first core of the processor in the active state and second information indicating occupancy of the first core in a first power saving state. The method includes generating an effective utilization based on the first information and the second information. The method includes setting a target frequency by performing a selected action of a first action including increasing the target frequency and a second action including decreasing the target frequency with respect to a current frequency of the processor based on the effective utilization. The selected action is selected according to the effective utilization. The method includes instructing the processor to operate the first core at the target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.