Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
US10552160B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | May 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing pipeline for processing instructions with instructions from multiple threads in flight concurrently may have control circuitry to detect a stalling event associated with a given thread. In response, at least one instruction of the given thread may be flushed from the pipeline, and the control circuitry may trigger fetch circuitry to reduce a fraction of the fetched instructions which are fetched from the given thread. A mechanism is also described to determine when to trigger a predetermined action when a delay in accessing information becomes greater than a delay threshold, and to update the delay threshold based on a difference between a return delay when the information is returned from the storage circuitry and the delay threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.