Array clocking in emulation
US10552184B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Feb 23, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | May 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Examples of techniques for emulating an application-specific integrated circuit (ASIC) array using a field programmable gate array (FPGA) are disclosed. In one example implementation according to aspects of the present disclosure, a method may include loading configuration information to the FPGA, wherein the configuration information is representative of configuration information of the ASIC. The method may further include emulating the ASIC using the FPGA loaded with the configuration information by applying a fast emulation clock signal to the FPGA. The fast emulation clock signal is a multiple of a system clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.