Mechanism to increase thread parallelism in a graphics processor
US10552211B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2016 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Nov 2, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus is described. The apparatus includes a plurality of execution threads having a first thread space configuration including a first plurality of rows of execution threads to process data in parallel, wherein each thread in a row is dependent on a top neighbor thread in a preceding row, partition logic to partition the plurality of execution threads into a plurality of banks, wherein each bank includes one or more of the first plurality of rows of execution threads and transform logic to transform the first thread space configuration to a second thread space configuration including a second plurality of rows of execution threads to enable the plurality of execution threads in each of the plurality of banks to operate in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.