Single command, multiple column-operation memory device
US10552310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jan 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/107
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.