Zero thrash cache queue manager
US10552343B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Nov 29, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various systems and methods for queue management in computer memory are described herein. A system for implementing a zero thrash cache queue manager includes a processor subsystem to: receive a memory access request for a queue; write data to a queue tail cache line in a cache when the memory access request is to add data to the queue, the queue tail cache line protected from being evicted from the cache; and read data from a current queue head cache line in the cache when the memory access request is to remove data from the queue, the current queue head cache line protected from being evicted from the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.