System and method for dynamic pipelining of direct memory access (DMA) transactions
US10552349B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a system for pipelining read transactions of a host computer from a storage module, including: transferring from a host computer to an accelerator a read list, including at least one pointer to a data block stored on the storage module, and a respective data block size; sending an acknowledgement to the host; fetching at least one data block by the accelerator from the storage module, and writing it to a staging buffer in a sequential order; sending at least one read request from the host computer to the accelerator, relating to at least one requested data block. If the data block is available on the staging buffer, then sending the corresponding data to the host from the staging buffer. Otherwise the read response is delayed until the requested data is fetched from the storage module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.