Superconducting system architecture for high-performance energy-efficient cryogenic computing
US10552756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2016 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Nov 10, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An energy efficient rapid single flux quantum (ERSFQ) logic register wheel includes a circular shift register having a plurality of destructive read out (DRO) cells. Each entry of the circular shift register includes a data block, a tag, and a valid bit. A compare and control logic is coupled to the circular shift register to compare a source specifier or a destination register specifier against a register tag stored in the wheel following each cycle of the register wheel. At least one or more read ports and at least one or more write ports are coupled to the circular shift register to write to or to read from a different entry each in the register wheel following each cycle of the register wheel. A RSFQ clearable FIFO with flushing and a crosspoint memory topology for integrating MRAM devices with ERSFQ circuits are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.