Techniques for robust reliability operation of a thin-film transistor (TFT) display
US10553177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2019 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Feb 6, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/028
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides devices and techniques for dynamically adjusting the bias voltage (V) levels (e.g., low level gate voltage (VGL) and high level gate voltage (VGH)) for display screens made with thin-film transistor (TFT) technology based on a display run time. Thus, as the positive bias temperature stress for the TFTs increases over the course of the display lifetime, features of the present disclosure adjust the bias voltage levels to maintain operation margin (e.g., the ratio between the high level gate voltage (VGH) value and the voltage value which the display can maintain with normal operation). By dynamically adjusting the bias voltage levels, the TFT displays of the present disclosure consume lower power than their conventional counterparts and improve the lifetime of the display itself.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.