Tailoring timing offsets during a programming pulse for a memory device
US10553286B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.