Selective NFET/PFET recess of source/drain regions
US10553492B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes forming an inter-layer dielectric over a first source/drain region and a second source/drain region. The first source/drain region and the second source/drain region are of n-type and p-type, respectively. The inter-layer dielectric is etched to form a first contact opening and a second contact opening, with the first source/drain region and the second source/drain region exposed to the first contact opening and the second contact opening, respectively. A process gas is used to etch back the first source/drain region and the second source/drain region simultaneously, and a first etching rate of the first source/drain region is higher than a second etching rate of the second source/drain region. A first silicide region and a second silicide region are formed on the first source/drain region and the second source/drain region, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.