Three-dimensional (3D) inductor-capacitor (LC) circuit
US10553530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2017 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Dec 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/0115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure relate to a three-dimensional (3D) inductor-capacitor (LC) circuit. The 3D LC circuit includes an inductor formed by a conductive ribbon of a defined height and a conductive sleeve conductively coupled to the conductive ribbon. The conductive sleeve and the conductive ribbon can generate a built-in capacitance(s) for the 3D LC circuit. In examples discussed herein, the conductive ribbon can also help reduce the skin effect of the inductor by distributing an electrical current across the defined height of the conductive ribbon. By generating the built-in capacitance(s) and distributing the electrical current across the defined height of the conductive ribbon, it is possible to reduce current crowding and improve quality factor (Q-factor) of the 3D LC circuit. As a result, it is possible to couple one or more 3D LC circuits to form a high performance radio frequency (RF) filter(s) for the fifth-generation (5G) wireless communication systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.