Semiconductor device having multiple semiconductor chips laminated together and electrically connected
US10553560B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2014 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | May 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip laminate in this semiconductor device has a structure consisting of a first semiconductor chip and a second semiconductor chip laminated together. The first semiconductor chip has a circuit-forming layer and a first bump electrode formed on one surface and a second bump electrode formed on the other surface. The second semiconductor chip has a circuit-forming layer and a third bump electrode formed on one surface and a fourth bump electrode formed on the other surface. The first semiconductor chip and the second semiconductor chip are laminated together such that the circuit-forming layer on the first semiconductor chip and the circuit-forming layer on the second semiconductor chip face each other and the first and third bump electrodes are electrically connected to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.