Load bypass slew control techniques
US10554204B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Feb 4, 2020 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05B45/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for an integrated slew-rate control circuit are provided. In certain examples, an adjustable, integrated slew-rate control circuit for a bypass transistor can provide three decades of adjustability. In an example, a slew-rate control circuit can include a load bypass transistor, a slew-rate control capacitor, electrically coupled between a conduction node of the load bypass transistor and a control node of the load bypass transistor, and a current mirror circuit. The current mirror circuit can include a sense transistor electrically coupled in series with the slew-rate control capacitor and the control node, and a mirror transistor electrically coupled between a power supply and the control node, to selectively provide, to or from the control node, a shunt current that bypasses the slew-rate control capacitor to limit a slew rate of a voltage at the conduction node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.