Array substrate motherboard, display panel motherboard, and fabricating method thereof
US10558101B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 13, 2019 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136263
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate motherboard includes a substrate including a plurality of gate lines, a plurality of gate line driving leads, a plurality of data lines, and a plurality of data line driving leads; a plurality of gate line testing leads; a plurality of data line testing leads and a plurality of data line driving leads; a plurality of gate line testing pads; a plurality of data line testing pads; and an insulating layer arranged between the data line testing leads and the data line driving leads in the trimming region. A respective one of the plurality of data line testing pads is connected with a respective one of the plurality of data line testing leads. A respective one of the plurality of data line driving leads is connected with one of the plurality of data line testing leads that penetrate through the insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.