Flash device lifetime monitor systems and methods
US10558369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2016 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.