Floating point to fixed point conversion
US10558428B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Apr 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1−1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a first shifter operable to receive a first significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a first output, wherein min{(ew−1), bitwidth(iw−2−sy)}≤k≤(ew−1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number; an inverting unit configured to invert the bit values of the exponent; a second shifter coupled to the inverting unit configured to receive a second significand input comprising a contiguous set of the most significant bits of the significand and configured to right-shift the input by a number of bits equal to the value represented by the p least significant bits of the inverted exponent to generate a second output, wherein min{(ew−1), bitwidth(fw)…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.