Scheduling heterogenous processors
US10558500B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2015 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Nov 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example computing device comprises a first processing unit having first capabilities, a second processing unit having second capabilities, and a shared memory accessible by the first processing unit and the second processing unit. The shared memory stores data objects in association with type information indicating the data type of the data objects. The example computing device further comprises an instruction set to, when executed by a processing unit of the computing device, select one of the first processing unit and the second processing unit to perform a computation of a particular type, using data of a particular type stored in the shared memory, wherein the selection is performed based on a predefined affinity of the first processing unit for the particular computation type and/or the particular data type and a predefined affinity of the second processing unit for the particular computation type and/or the particular data type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.