Memory device, the control method of the memory device and the method for controlling the memory device
US10558594B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | May 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An asynchronous NAND-type memory device includes a circuit configured to perform an operation based on a signal, a first pin configured to obtain an operation control signal, a second pin configured to output a data output reference signal, and a third pin configured to output data in synchronization with the data output reference signal. The circuit is provided such that the first pin obtains, from the external device, the operation control signal that is transitioned at a second time point after a first time point at which the memory device enters into a ready state, the second pin outputs the data output reference signal, which is transitioned at a third time point that is later than the second time point by a predetermined time interval, and the third pin outputs the data in synchronization with the operation control signal which is periodically transitioned, from the third time point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.