Bitline-driven sense amplifier clocking scheme
US10559352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Sep 18, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.