Three-dimensional semiconductor devices
US10559590B2 · kind B2 · utility
0Cited by
5References
14Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 28, 2018 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Jun 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.