Array substrate and method for manufacturing the same
US10559601B2 · kind B2 · utility
1Cited by
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18Claims
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Key dates
| Filing date | Jun 23, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Oct 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a thin film transistor and comprises at least a first region and a second region. A thickness of an active layer of the thin film transistor in the first region is different from that of an active layer of the thin film transistor in the second region. A ratio of the overlapped area between the source electrode or the drain electrode and the active layer of the thin film transistor to the thickness of the active layer is kept uniform over the first region and the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.