Semiconductor devices having vertical transistors with aligned gate electrodes
US10559673B2 · kind B2 · utility
0Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2019 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Feb 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an active pillar on a substrate. A first source/drain region is disposed at a top end of the active pillar and has a greater width than the active pillar. A first insulating layer is disposed on a sidewall of the active pillar and a second insulating layer is disposed on at least a bottom surface of the first source/drain region. A gate electrode is disposed on the first insulating layer and the second insulating layer. A second source/drain region is disposed in the substrate at a bottom end of the active pillar. Methods of fabrication are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.