Pin array including segmented pins for forming selectively plated through holes
US10561020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2017 |
| Grant date | Feb 11, 2020 |
| Priority date | — |
| Expiry date | Oct 14, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process includes utilizing a pin array that includes multiple segmented pins for forming selectively plated through holes. The process includes forming a PCB laminate structure that includes multiple spinel-doped core layers and multiple through holes. Each spinel-doped core layer includes a heat-activated spinel material incorporated into a dielectric material. The process includes aligning individual segmented pins of a pin array with corresponding through holes of the PCB laminate structure, where each segmented pin includes heated segment(s) and insulating segment(s). The process includes inserting the segmented pins of the pin array into the corresponding through holes and generating heat within each heated pin segment that is sufficient to form metal nuclei sites in selected regions of the spinel-doped core layers adjacent to portions of the through holes that contain the heated pin segments. The metal nuclei sites function as seed layers to enable formation of selectively plated through holes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.