Communication between dataflow processing units and memories
US10564929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Apr 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combination of memory units and dataflow processing units is disclosed for computation. A first memory unit is interposed between a first dataflow processing unit and a second dataflow processing unit. Operations for a dataflow graph are allocated across the first dataflow processing unit and the second dataflow processing unit. The first memory unit passes data between the first dataflow processing unit and the second dataflow processing unit to execute the dataflow graph. The first memory unit is a high bandwidth, shared memory device including a hybrid memory cube. The first dataflow processing unit and second dataflow processing unit include a plurality of circular buffers containing instructions for controlling data transfer between the first dataflow processing unit and second dataflow processing unit. Additional dataflow processing units and additional memory units are included for additional functionality and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.