Method of synchronizing host and coprocessor operations via FIFO communication
US10565036B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2019 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4247
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of synchronizing thread execution of a host and one or more coprocessors includes writing by the host of an event command and at least one coprocessor instruction to a FIFO and comparing of the event command with a current event register of the coprocessor until they match, whereupon the FIFO entries are popped and the instructions are forwarded to the coprocessor for execution. A plurality of entry groups can be written to the FIFO, each beginning with an event command. The instructions can direct the coprocessor to exchange data with shared memory and apply its thread to the received data. The processors and shared memory can be linked by a ring-type bus having a controller that performs the comparison, popping, and instruction forwarding. The coprocessor clears the current event register during thread execution, and then writes an event command to the register when processing is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.