Relay consistent memory management in a multiple processor system
US10565112B2 · kind B2 · utility
43Cited by
17References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Apr 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for memory management are described. In a disclosed embodiment, a system has a first and a second processor, with each processor able to access a memory system. A first work unit is received for execution by the first processor, with the memory system being accessed. A second work unit is generated for execution by a second processor upon execution of a first work unit. Only after the memory system is updated does processing of the second work unit by the second processor occur. This work unit message based ordering provides relay consistency for memory operations of multiple processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.