Compute node security
US10565129B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | May 2, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In various examples a compute node is described. The compute node has a central processing unit which implements a hardware transactional memory using at least one cache of the central processing unit. The compute node has a memory in communication with the central processing unit, the memory storing information comprising at least one of: code and data. The compute node has a processor which loads at least part of the information, from the memory into the cache. The processor executes transactions using the hardware transactional memory and at least the loaded information, such that the processor ensures that the loaded information remains in the cache until completion of the execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.