Patent · US Active

Field-effect transistor placement optimization for improved leaf cell routability

US10565340B2 · kind B2 · utility

0Cited by

5References

3Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Iris Maria Leefken · Waldenbuch, DE
Silke Penth · Holzgerlingen, DE
Michael Stetter · Fishkill, US
Tobias Werner · Holzgerlingen, DE

Key dates

Filing date	Nov 14, 2017
Grant date	Feb 18, 2020
Priority date	—
Expiry date	Nov 14, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2111/04
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.