System for and method of fabricating an integrated circuit
US10565348B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2019 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Jul 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit is disclosed. The method includes defining a via grid, generating a first layout design of the integrated circuit based on at least the via grid or design criteria, generating a standard cell layout design of the integrated circuit, generating a via color layout design of the integrated circuit based on the first layout design and the standard cell layout design, performing a color check on the via color layout design based on design rules, and fabricating the integrated circuit based on at least the via color layout design. The first layout design has a first set of vias arranged in first rows and first columns based on the via grid. The standard cell layout design has standard cells and a second set of vias arranged in the standard cells. The via color layout design has a third set of vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.