Block device modeling
US10565501B1 · kind B1 · utility
1Cited by
14References
21Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 19, 2013 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Jan 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for formally expressing whether sequences of operations performed on block storage devices are sequential or random. In embodiments, determinations of whether these sequences of operations are sequential or random may be used to predict latencies involved with running particular workloads, and to predict representative workloads for particular latencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.