Memory control device and memory control method
US10566065B2 · kind B2 · utility
1Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Sep 20, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control device includes a memory and a controller. The memory includes a plurality of memory blocks. The controller is coupled to the memory and configured to select a first memory block from the memory blocks and program data into the first memory block. When the memory control device is deactivated and re-activated, the controller is further configured to read a voltage distribution of the first memory block to determine a deactivation interval, and determine a reference time according to the deactivation interval and an initial time, and the voltage distribution of the first memory block correspond to the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.