Method for alleviating etching defect of salicide barrier layer
US10566203B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Dec 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for alleviating an etching defect of a salicide barrier layer is disclosed. The salicide barrier layer includes a first barrier layer, a second barrier layer and a third barrier layer. When the salicide barrier layer is being etched, the third barrier layer is removed during first etching. In this case, the second barrier layer is used as an etch stop layer, and the second barrier layer is removed during second etching. In this case, the first barrier layer is used as an etch stop layer, the first barrier layer is removed during third etching. The salicide barrier layer is divided into three layers, the second barrier layer and the first barrier layer are respectively used as an etch stop layer, so that the third barrier layer and the second barrier layer can be prevented from being over-etched, thereby effectively avoiding defects caused by over-etching and alleviating device performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.