Power semiconductor device and method for manufacturing the same
US10566422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Aug 3, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/126
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power semiconductor device includes a drain region and a source region disposed on a substrate, a gate insulating layer and a gate electrode disposed on the substrate and disposed between the drain region and the source region, a protection layer in contact with a top surface of the substrate and a top surface of the gate electrode, a source contact plug connected to the source region, a drain contact plug connected to the drain region, and a field plate plug in contact with the protection layer, wherein a width of the field plate plug is greater than a width of the source contact plug or a width of the drain contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.