Methods, systems and computer readable media for evaluating link or component quality using synthetic forward error correction (FEC)
US10567123B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for evaluating link or component quality using synthetic forward error correction (FEC) includes generating a bit sequence. The method further includes transmitting the bit sequence over a link or through a component under test without adding FEC to the bit sequence. The method further includes receiving a bit sequence transmitted over the link or through the component. The method further includes determining locations of bit errors in the received bit sequence. The method further includes determining locations of synthetic FEC codeword and symbol boundaries in the received bit sequence for the synthetic FEC algorithm against which link or component quality is being evaluated. The method further includes identifying symbol and codeword errors for the synthetic FEC algorithm based on the locations of bit errors in received bit sequence. The method further includes outputting an indication of link or component quality based on the symbol and codeword errors identified for the synthetic FEC algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.