High frame rate video compatible with existing receivers and amenable to video decoder implementation
US10567703B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Jul 21, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44029
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for achieving a high frame rate video with compatibility for existing receivers without depending bitstream encoding are provided herein. For example, an apparatus comprises: a memory; and one or more processors configured to execute instructions stored in the memory. The instructions comprise: receiving a first bitstream having a first packet identifier (“PID”) and a second bitstream having a second PID; decoding the first bitstream and the second bitstream; and interleaving the decoded first bitstream and the decoded second bitstream to form a high frame rate video signal, wherein the high frame rate video signal has a frame rate equal to the sum of the frame rate of the decoded first bitstream and the decoded second bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.