Transform hardware architecture for video coding
US10567800B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2017 |
| Grant date | Feb 18, 2020 |
| Priority date | — |
| Expiry date | Aug 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/423
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for performing transformation on video data. A transform circuit may receive M sample values of the video data from a pre-transform buffer, and process the M sample values with N computation units of the transform circuit to generate intermediate values. Processing the M sample values to generate the intermediate values includes feeding back temporary values from output of one or more of the N computation units to input of one or more of the N computation units. The transform circuit may store a first set of the intermediate values in a transpose buffer, and store a second set of the intermediate values in the pre-transform buffer that are to be later retrieved for storage in the transpose buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.