Redundant fault detection device and method
US10571303B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 3, 2018 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Apr 3, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01D2205/771
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit for error detection comprises an input for receiving two signals, in which a first signal is representative of a physical quantity in a first range and a second signal is representative of the physical quantity in a second range. The first range and second range are different ranges that overlap. The circuit comprises a processor configured to detect an inconsistency between the two signals by taking said first and second range into account, in which this inconsistency is indicative of an error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.