Method for manufacturing array substrate and array substrate
US10571736B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Sep 6, 2015 |
| Grant date | Feb 25, 2020 |
| Priority date | — |
| Expiry date | Sep 6, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/136231
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method for manufacturing an array substrate and an array substrate are disclosed. The method comprises the steps of forming a plurality of control electrodes on a baseplate, and forming a color-resist region between two adjacent control electrodes, wherein the color-resist region is a first color-resist region, a second color-resist region, a third color-resist region, and a fourth color-resist region in sequence; forming a first color-resist in the first color-resist region, forming a second color-resist in the second color-resist region, and forming a third color-resist in the third color-resist region; and coating the baseplate on which the control electrodes, the first color-resist, the second color-resist, and the third color-resist are formed and the fourth color-resist region with a transparent photoresist so as to form a flat layer. In the method according to the present disclosure, the production efficiency of the array substrate can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.